This invention relates to a method for fabricating a power semiconductor device with a low forward voltage drop.
In the past, processing a power semiconductor device to reduce its forward voltage drop was incompatible with certain passivation materials. The temperatures required for conventional techniques were often too high for certain passivation materials, particularly those with good high voltage isolation characteristics, e.g., polymers. It was therefore difficult to fabricate a power semiconductor device which had both a low forward voltage drop and good high voltage isolation.
Moreover, traditional potting and encapsulation techniques have proven insufficient for providing protection from environmental contamination for semiconductor power devices. Plastic encapsulated devices develop contaminating byproducts due to the polymerization process. Additionally, the basic components of plastics often contain ionic contaminants like K+ and Na+. Potting compounds used in module assembly create similar problems. Generally, plastic encapsulated devices are not hermetically sealed, and are therefore prone to degradation in severe environmental conditions. Some methods were developed in which, for example, a semiconductor die was coated during the assembly process by a highly pure rubber which was not masked, but applied over the die in a module after die attach, after wire bonding, or just before applying the final encapsulation. However, such a technique requires additional "post-fab" processing.
Therefore, there is a need for a fabrication method which uses polymer passivation in conjunction with power device processing to create a low forward voltage drop. There is also a need to provide semiconductor devices with additional protection from environmental contaminants with a process which can be integrated into the fabrication process.